参数资料
型号: M1A3PE1500-2FG676
厂商: Microsemi SoC
文件页数: 129/162页
文件大小: 0K
描述: IC FPGA 1KB FLASH 1.5M 676-FBGA
标准包装: 40
系列: ProASIC3E
RAM 位总计: 276480
输入/输出数: 444
门数: 1500000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
ProASIC3E Flash Family FPGAs
Revision 13
2-55
Table 2-85 Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
HH, DOUT
tOSUD
Data Setup Time for the Output Data Register
FF, HH
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
GG, HH
tOHE
Enable Hold Time for the Output Data Register
GG, HH
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
LL, DOUT
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
LL, HH
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
LL, HH
tOECLKQ
Clock-to-Q of the Output Enable Register
HH, EOUT
tOESUD
Data Setup Time for the Output Enable Register
JJ, HH
tOEHD
Data Hold Time for the Output Enable Register
JJ, HH
tOESUE
Enable Setup Time for the Output Enable Register
KK, HH
tOEHE
Enable Hold Time for the Output Enable Register
KK, HH
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
II, EOUT
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
II, HH
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
II, HH
tICLKQ
Clock-to-Q of the Input Data Register
AA, EE
tISUD
Data Setup Time for the Input Data Register
CC, AA
tIHD
Data Hold Time for the Input Data Register
CC, AA
tISUE
Enable Setup Time for the Input Data Register
BB, AA
tIHE
Enable Hold Time for the Input Data Register
BB, AA
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
DD, EE
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
DD, AA
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
DD, AA
Note: *See Figure 2-26 on page 2-54 for more information.
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