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| 型号： | M2004-22I622.0800 |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 1/10页 |
| 文件大小： | 403K |
| 代理商： | M2004-22I622.0800 |
Preliminar y Inf o r m ation
M2004-x2 Datasheet Rev 1.3
Revised 10Sep2003
Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.icst.com ● tel (508) 852-5400
M2004-x2
FREQUENCY TRANSLATION PLL FAMILY
GENERAL DESCRIPTION
The M2004 variants -22, -32, -42, and -52 are VCSO
(Voltage Controlled SAW Oscillator)
based clock generator PLLs
designed for clock frequency
translation and jitter attenuation in
a high-speed data communications
system. The clock multiplication
ratio and output divider ratio are
pin selectable. External loop components allow the
tailoring of PLL loop response. Based on the M2004-02,
these device variants add the Hitless Switching with
Phase Build-out (HS/PBO) feature. HS/PBO ensures
that reference clock reselection does not disrupt the
output clock. In addition, a fixed Narrow Loop
Bandwidth feature (Fixed NBW) is included in the some
of the device variants.
FEATURES
◆ Pin-compatible with M2004-02/-12, these new product
variants offer new functions
◆ Hitless Switching with Phase Build-out to ensure
SONET/SDH MTIE and TDEV compliance during
reference clock reselection
◆ Fixed Narrow Loop Bandwidth feature available
◆ Ideal for OC-48/192 data clock
◆ Integrated SAW (surface acoustic wave) delay line
◆ VCSO frequency from 300 to 700MHz **
◆ Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable configuration
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Industrial temperature available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
* This sheet covers only parts numbered M2004-22, -32, -42, -52.
See M2004-02/-12 Product Data Sheet for M2004-02 & M2004-12.
** Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Input / Output Frequency Combinations
Input (MHz) VCSO ** (MHz) Output (MHz)
Application
19.44
622.08
77.76
OC-12 / 48
/192
77.76
311.04
155.52
622.08
Device Variants and Corresponding Functions
Variant
Hitless Switching /
Phase Build-out Triggered by
Fixed
NBW
Phase Transient Mux Reselection
M2004-02
no
M2004-12
Yes
no
M2004-22
no
Yes
M2004-32
Yes
M2004-42
no
Yes
no
M2004-52
no
Yes
M2004-x2 Frequency Translation PLL Family
*
相关PDF资料 |
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| M2004-22-622.0800LF | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
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