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| 型号： | M2061-13I625.0000 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 8/12页 |
| 文件大小： | 477K |
| 代理商： | M2061-13I625.0000 |
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
5 of 12
Revised 30Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminar y In f o r m atio n
The M206x Series includes a Loss of Lock (LOL)
indicator, which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide SONET/
SDH MTIE and TDEV compliance during a reference
clock reselection.
Input Reference Clocks
Two clock reference inputs and a selection mux is
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Configuration of a single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50k
to Vcc and 50k to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
.
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127
and 82
resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M2060/61/62 and M2065/66/67 are complete clock
PLLs. They use a phase detector and configurable
dividers to synchronize the output of the VCSO with the
selected reference clock.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is typi-
cally about 200 ppm above or below the VCSO center
frequency. See “APR, VCSO Absolute Pull-Range” row,
in the AC Characteristics table on pg. 11.
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
The relationship between the nominal VCSO center
frequency (Fvcso), the Mfin divider, the Mfec divider,
the Rfec divider, and the input reference frequency (Fin)
is:
MUX
0
REF_SEL
1
VCC
50k
VCC
50k
LVCMOS/
LVTTL
LVPECL
50k
VCC
82
127
VCC
82
127
X
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
Fvcso
Fin
Mfin
×
Mfec
Rfec
--------------
×
=
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