参数资料
型号: M24C16-WMB6TP
厂商: 意法半导体
元件分类: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS
文件页数: 7/25页
文件大小: 449K
代理商: M24C16-WMB6TP
7/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the Read/Write bit
(RW) reset to 0. The device acknowledges this, as
shown in
Figure 8.
, and waits for an address byte.
The device responds to the address byte with an
acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is triggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in
Figure 7.
, and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in
Figure 8.
.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
S
S
Byte Write
DEV SEL
BYTE ADDR
DATA IN
WC
S
Page Write
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
WC
DATA IN 3
AI02803C
Page Write
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
NO ACK
R/W
ACK
ACK
NO ACK
NO ACK
R/W
NO ACK
NO ACK
相关PDF资料
PDF描述
M24C16-WMN3 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMN3G The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMN3P The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMN3TG The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMN3TP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
相关代理商/技术参数
参数描述
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M24C16WMN6P 制造商:STMicroelectronics 功能描述:
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