参数资料
型号: M27C64A-15K6X
厂商: STMICROELECTRONICS
元件分类: PROM
英文描述: 8K X 8 OTPROM, 150 ns, PQCC32
封装: PLASTIC, LCC-32
文件页数: 7/14页
文件大小: 107K
代理商: M27C64A-15K6X
M27C64A
2/14
Figure 2B. Pin Connections
AI00836
NC
A8
A10
Q4
17
A0
NC
Q0
Q1
Q2
DU
Q3
A6
A3
A2
A1
A5
A4
9
P
A9
1
V
PP
A11
Q6
A7
Q7
32
DU
V
CC
M27C64A
A12
NC
Q5
G
E
25
V
SS
Figure 2A. DIP Connections
Q2
VSS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
E
Q3
A11
Q7
Q6
Q4
NC
P
A12
A4
VPP
VCC
A7
AI00835
M27C64A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
20
19
18
17
16
15
A6
A5
A9
A8
28
27
26
25
24
23
22
21
Table 1. Signal Names
A0-A12
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
DU
Don’t Use
DEVICE OPERATION
The modes of operation of the M27C64A are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode
The M27C64A has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
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