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参数资料
| 型号： | M27C800-120M6TR |
| 厂商： | 意法半导体 |
| 英文描述： | Octal Buffer/Driver With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 8兆1兆x8或512KB的x16紫外线存储器和OTP存储器 |
| 文件页数： | 6/18页 |
| 文件大小： | 171K |
| 代理商： | M27C800-120M6TR |
M27C800
6/18
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 5V ± 5% or 5V ± 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Table 8B. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 5V ± 5% or 5V ± 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
Test Condition
M27C800
Unit
-50
(3)
-70
-90
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output
Valid
E = V
IL
, G = V
IL
50
70
90
ns
t
BHQV
t
ST
BYTE High to Output
Valid
E = V
IL
, G = V
IL
50
70
90
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
50
70
90
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
30
35
45
ns
t
BLQZ(2)
t
STD
BYTE Low to Output Hi-Z
E = V
IL
, G = V
IL
30
30
30
ns
t
EHQZ(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
30
0
30
0
30
ns
t
GHQZ(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
30
0
30
0
30
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
5
5
5
ns
t
BLQX
t
OH
BYTE Low to Output
Transition
E = V
IL
, G = V
IL
5
5
5
ns
Symbol
Alt
Parameter
Test Condition
M27C800
Unit
-100
-120/150
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
100
120
ns
t
BHQV
t
ST
BYTE High to Output Valid
E = V
IL
, G = V
IL
100
120
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
100
120
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
50
60
ns
t
BLQZ(2)
t
STD
BYTE Low to Output Hi-Z
E = V
IL
, G = V
IL
40
50
ns
t
EHQZ(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
40
0
50
ns
t
GHQZ(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
40
0
50
ns
t
AXQX
t
OH
Address Transition to Output Transition
E = V
IL
, G = V
IL
5
5
ns
t
BLQX
t
OH
BYTE Low to Output Transition
E = V
IL
, G = V
IL
5
5
ns
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