参数资料
型号: M27C800-120XF1TR
厂商: 意法半导体
英文描述: Octal Buffer/Driver With 3-State Outputs 20-TSSOP -40 to 85
中文描述: 8兆1兆x8或512KB的x16紫外线存储器和OTP存储器
文件页数: 9/18页
文件大小: 171K
代理商: M27C800-120XF1TR
9/18
M27C800
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25 °C; V
CC
= 6.25V ± 0.25V; V
PP
= 12.5V ± 0.25V)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25 °C; V
CC
= 6.25V ± 0.25V; V
PP
= 12.5V ± 0.25V)
Symbol
Alt
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
CC
±1
μ
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2.4
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –2.5mA
3.5
V
V
ID
A9 Voltage
11.5
12.5
V
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
2
μs
t
QVEL
t
DS
Input Valid to Chip Enable Low
2
μs
t
VPHAV
t
VPS
V
PP
High to Address Valid
2
μs
t
VCHAV
t
VCS
V
CC
High to Address Valid
2
μs
t
ELEH
t
PW
Chip Enable Program Pulse Width
45
55
μs
t
EHQX
t
DH
Chip Enable High to Input Transition
2
μs
t
QXGL
t
OES
Input Transition to Output Enable Low
2
μs
t
GLQV
t
OE
Output Enable Low to Output Valid
120
ns
t
GHQZ(2)
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address
Transition
0
ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C800 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposition to ultravio-
let light (UVEPROM). The M27C800 is in the pro-
gramming mode when V
PP
input is at 12.5V, G is
at V
IH
and E is pulsed to V
IL
. The data to be pro-
grammed is applied to 16 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V
CC
is specified to be
6.25V ± 0.25V.
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