参数资料
型号: M27V201-150XF1TR
厂商: 意法半导体
英文描述: 2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
中文描述: 2兆位的256Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储器
文件页数: 5/15页
文件大小: 103K
代理商: M27V201-150XF1TR
5/15
M27V201
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70
°
C or –40 to 85
°
C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°
C or –40 to 85
°
; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±
10
μ
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±
10
μ
A
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
– 0.2V, V
CC
3.6V
20
μ
A
I
PP
Program Current
V
PP
= V
CC
10
μ
A
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400
μ
A
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
Vcc –0.7V
V
Symbol
Alt
Parameter
Test Condition
M27V201
Unit
-120
-150
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
120
150
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
120
150
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
50
60
ns
t
EHQZ(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
40
0
50
ns
t
GHQZ(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
40
0
50
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
0
0
ns
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7
μ
F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.Thepurpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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