参数资料
型号: M28C256-12KA1T
厂商: 意法半导体
元件分类: EEPROM
英文描述: 256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
中文描述: 256千位(的32KB × 8)与软件数据保护并行的EEPROM
文件页数: 4/21页
文件大小: 132K
代理商: M28C256-12KA1T
Mode
E
G
W
DQ0 - DQ7
Read
V
IL
V
IL
V
IH
Data Out
Write
V
IL
V
IH
V
IL
Data In
Standby / Write Inhibit
V
IH
X
X
Hi-Z
Write Inhibit
X
X
V
IH
Data Out or Hi-Z
Write Inhibit
X
V
IL
X
Data Out or Hi-Z
Output Disable
X
V
IH
X
Hi-Z
Notes:
1. X = V
IH
or V
IL.
Table3. OperatingModes
(1)
The devices offer fast access time with low power
dissipationand requiresa 5V or 3V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation.A
Software Data Protection (SDP) is also possible
using the standard JEDECalgorithm.
PIN DESCRIPTION
Addresses (A0-A14).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
lowto enableall read/writeoperations.When Chip
Enable is high, power consumptionis reduced.
Output Enable(G).
The Output Enableinput con-
trols the dataoutput buffers andis usedto initiate
read operations.
DataIn/Out(DQ0-DQ7).
Datais writtento orread
from the memory through the I/O pins.
WriteEnable(W).
TheWriteEnableinputcontrols
the writingof datato the memory.
OPERATIONS
Write Protection
In orderto preventdata corruptionand inadvertent
writeoperations;an internalV
CC
comparatorinhib-
its Write operationsif V
CC
is belowVWI (see Table
7andTable9).Accessto thememoryinwritemode
is allowed after a power-upas specifiedin Table 7
and Table 9.
Read
The device is accessedlike a static RAM. WhenE
and G are low with W high, the data addressedis
presented on the I/O pins. The I/O pins are high
impedancewhen either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.Thedevice supportsboth E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslastand theData on the risingedge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accord-
ingly.
Page Write
Page write allows up to 64 bytes within the same
page to be consecutivelylatched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the samefor all bytes;if not,the
Page Write instruction is not executed. The page
writecan be initiatedby any byte write operation.
A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the t
WHWH
value (see Table 12 and
Table 13).
If this period of time exceedsthe t
WHWH
value, the
internalprogrammingcyclewillstart.Onceinitiated
thewrite operationis internallytimed untilcomple-
tion and the status of the Data Polling and the
ToggleBit functionson DQ7and DQ6 is controlled
accordingly.
DESCRIPTION
(Cont’d)
4/21
M28256
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M28C256-12KA6T 256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
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M28C256-12KA6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
M28C256-12MS1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
M28C256-12MS6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
M28C256-12NS1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection
M28C256-12NS6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection