参数资料
型号: M28LV64-200K1
厂商: 意法半导体
元件分类: DRAM
英文描述: 64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION
中文描述: 64K的8K的× 8低电压并联EEPROM,带有软件数据保护
文件页数: 5/18页
文件大小: 127K
代理商: M28LV64-200K1
MicrocontrollerControl Interface
The M28LV64 provides two write operation status
bitsandonestatuspinthatcanbeusedtominimize
the system writecycle. Thesesignals areavailable
on the I/O port bits DQ7 or DQ6 of the memory
duringprogrammingcycleonly, oras theRBsignal
on a separate pin.
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure4. Status Bit Assignment
Data Polling bit (DQ7).
During the internal write
cycle, any attemptto read the last byte writtenwill
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6).
The M28LV64 offers another
way for determining when the internal write cycle
iscompleted.DuringtheinternalErase/Writecycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequentattempts to
read the memory. When the internal cycle is com-
pleted the togglingwill stopand the device will be
accessiblefor a new Read or Writeoperation.
Page Load Timer Status bit (DQ5)
. In the Page
Write mode data may be latchedby E or W up to
100
μ
s after the previous byte. Up to 64 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (t
PLTS
).
DQ5 Low indicates the timer is running, High indi-
cates time-out after which the write cycle will start
and no new data may be input.
Ready/Busy pin (available only on the
M28LV64).
TheRB pinprovidesa signalat itsopen
drain output which is low during the erase/write
cycle,butwhichis releasedatthe completionof the
programmingcycle.
Software Data Protection
The M28LV64 offers a software controlled write
protection facility that allows the user to inhibit all
write modesto thedevice includingthe ChipErase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occurdue to uncontrolledbus conditions.
The M28LV64isshippedasstandardinthe”unpro-
tected” state meaning that the memory contents
can be changed as required by theuser. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
Toenable the SoftwareData Protection(SDP) the
devicerequirestheusertowrite (withaPageWrite)
three specificdata bytes to threespecific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specificdatabytesintosixdifferentlocationsasper
Figure 6 (with a Page Write). This complexseries
ensures that the user will never enable or disable
the SoftwareData Protectionaccidentally.
DP =Data Polling
TB = ToggleBit
PLTS = Page Load Timer Status
5/18
M28LV64
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