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参数资料
型号： M29DW323DB70N6F
厂商： 意法半导体
英文描述： 32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory
中文描述： 32兆位4Mb的x8或功能的2Mb x16插槽，双行8时24分，启动块3V电源快闪记忆体
文件页数： 11/49页
文件大小： 818K
代理商： M29DW323DB70N6F
11/49
M29DW323DT, M29DW323DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
IH
. When BYTE is Low, V
IL
, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
PP/
Write Protect (V
PP
/WP).
The
Protect
pin provides two functions. The V
PP
func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the Dou-
ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When V
PP
/Write Protect is Low, V
IL
, the memory
protects the two outermost boot blocks; Program
V
PP
/Write
and Erase operations in these blocks are ignored
while V
PP
/Write Protect is Low, even when RP is
at V
ID
.
When V
PP
/Write Protect
is High, V
IH
, the memory
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase oper-
ations can now modify the data in these blocks un-
less the blocks are protected using Block
Protection.
When V
PP
/Write Protect is raised to V
PP
the mem-
ory automatically enters the Unlock Bypass mode.
When V
PP
/Write Protect returns to V
IH
or V
IL
nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
PP
from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
IH
to V
PP
and from V
PP
to V
IH
must be slower
than t
VHVPP
, see Figure 16.
Never raise V
PP
/Write Protect to V
PP
from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
PP
/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1μF capacitor should be connected be-
tween the V
PP
/Write Protect pin and the V
SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
PP
.
Reset/Block Temporary Unprotect (RP).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
PP
/WP is at V
IL
, then the two outer-
most boot blocks will remain protected even if RP
is at V
ID
.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 16 and Figure 15, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
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相关代理商/技术参数
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M29DW323DB70N6T 功能描述:闪存 32M (4Mx8 or 2Mx16) RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel
M29DW323DB70ZA1 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory
M29DW323DB70ZA1E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory
M29DW323DB70ZA1F 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory
M29DW323DB70ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory
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