参数资料
型号: M29DW640D70N6E
厂商: 意法半导体
英文描述: 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
中文描述: 64兆位(8兆x8或4Mb的x16插槽,多行,页,引导块)3V电源快闪记忆体
文件页数: 11/56页
文件大小: 942K
代理商: M29DW640D70N6E
11/56
M29DW640D
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
, and
Table
1., Signal Names
, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A21).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Data Inputs/Outputs (DQ8-DQ14).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
IH
. When BYTE is Low, V
IL
, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
PP/
Write Protect (V
PP
/WP).
The
Protect
pin provides two functions. The V
PP
func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the multi-
ple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
V
PP
/Write
When V
PP
/Write Protect is Low, V
IL
, the memory
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V
PP
/Write Protect is Low, even when RP is
at V
ID
.
When V
PP
/Write Protect
is High, V
IH
, the memory
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When V
PP
/Write Protect is raised to V
PP
the mem-
ory automatically enters the Unlock Bypass mode.
When V
PP
/Write Protect returns to V
IH
or V
IL
nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
PP
from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
IH
to V
PP
and from V
PP
to V
IH
must be slower
than t
VHVPP
, see Figure
18
.
Never raise V
PP
/Write Protect to V
PP
from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
PP
/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1μF capacitor should be connected be-
tween the V
PP
/Write Protect pin and the V
SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
PP
.
Reset/Block Temporary Unprotect (RP).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
PP
/WP is at V
IL
, then the four outer-
most boot blocks will remain protected even if RP
is at V
ID
.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table
19
and
Figure 17., Reset/
Block Temporary Unprotect AC Waveforms
.
Holding RP at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
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