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参数资料
型号： M29DW640D90N1
厂商： 意法半导体
英文描述： CONNECT-CRIMP STRT PLUG L/C
中文描述： 64兆位（8兆x8或4Mb的x16插槽，多行，页，引导块）3V电源快闪记忆体
文件页数： 16/56页
文件大小： 942K
代理商： M29DW640D90N1
M29DW640D
16/56
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper-
ations, the final Write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
Programming can be suspended and then re-
sumed by issuing a Program Suspend command
and a Program Resume command, respectively
(see
Program Suspend Command
and
Program
Resume Command
paragraphs).
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array. See the section on the Status Reg-
ister for more details. Typical program times are
given in Table
7
.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Fast Program Commands
There are five Fast Program commands available
to improve the programming throughput, by writing
several adjacent Words or Bytes in parallel.
Double Word Program Command.
This
used to write two adjacent Words in x16 mode, in
parallel. The addresses of the two Words must dif-
fer only in A0.
Three bus write cycles are necessary to issue the
command.
The first bus cycle sets up the command.
The second bus cycle latches the Address and
the Data of the first Word to be written.
The third bus cycle latches the Address and
the Data of the second Word to be written and
starts the Program/Erase Controller.
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Quadruple Word Program Command.
This is
used to write a page of four adjacent Words, in x16
mode, in parallel. The addresses of the four Words
must differ only in A1 and A0.
Five bus write cycles are necessary to issue the
command.
The first bus cycle sets up the command.
The second bus cycle latches the Address and
the Data of the first Word to be written.
The third bus cycle latches the Address and
the Data of the second Word to be written.
The fourth bus cycle latches the Address and
the Data of the third Word to be written.
The fifth bus cycle latches the Address and the
Data of the fourth Word to be written and starts
the Program/Erase Controller.
Double Byte Program Command.
This is used
to write two adjacent Bytes in x8 mode, in parallel.
The addresses of the two Bytes must differ only in
DQ15A-1.
Three bus write cycles are necessary to issue the
command.
The first bus cycle sets up the command.
The second bus cycle latches the Address and
the Data of the first Byte to be written.
The third bus cycle latches the Address and
the Data of the second Byte to be written and
starts the Program/Erase Controller.
Quadruple Byte Program Command.
This
used to write four adjacent Bytes in x8 mode, in
parallel. The addresses of the four Bytes must dif-
fer only in A0, DQ15A-1.
Five bus write cycles are necessary to issue the
command.
The first bus cycle sets up the command.
The second bus cycle latches the Address and
the Data of the first Byte to be written.
The third bus cycle latches the Address and
the Data of the second Byte to be written.
The fourth bus cycle latches the Address and
the Data of the third Byte to be written.
The fifth bus cycle latches the Address and the
Data of the fourth Byte to be written and starts
the Program/Erase Controller.
Octuple Byte Program Command.
This is used
to write eight adjacent Bytes, in x8 mode, in paral-
lel. The addresses of the eight Bytes must differ
only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the
command.
The first bus cycle sets up the command.
The second bus cycle latches the Address and
the Data of the first Byte to be written.
The third bus cycle latches the Address and
the Data of the second Byte to be written.
The fourth bus cycle latches the Address and
the Data of the third Byte to be written.
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相关PDF资料
PDF描述
M29DW640D70ZA6T 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA6F 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA6E 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA6 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA1T 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
相关代理商/技术参数
参数描述
M29DW640D90N1E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D90N1F 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D90N1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D90N6 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D90N6E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
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