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参数资料
型号： M30102F3FP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数： 103/166页
文件大小： 2060K
代理商： M30102F3FP
Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
38
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction
FFFDC16 to FFFDF16
Interrupt on UND instruction
Overflow
FFFE016 to FFFE316
Interrupt on INTO instruction
BRK instruction
FFFE416 to FFFE716
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match
FFFE816 to FFFEB16
There is an address-matching interrupt enable bit
Single step (Note)
FFFEC16 to FFFEF16
Do not use
Oscillation stop detection/
FFFF016 to FFFF316
watchdog timer
________
DBC (Note)
FFFF416 to FFFF716
Do not use
UART0 receive (Note)
FFFF816 to FFFFB16
Do not use
Reset
FFFFC16 to FFFFF16
Table 1.12.1. Interrupt and fixed vector address
Note: Interrupts used for debugging purposes only.
Mid address
Low address
0 0 0 0
High address
0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.12.2 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.12.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Figure 1.12.2. Format for specifying interrupt vector addresses
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