- 您现在的位置：买卖IC网 > PDF目录45012 > M30260M6A-XXXGP-D5 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP48 PDF资料下载
参数资料
| 型号： | M30260M6A-XXXGP-D5 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 6/26页 |
| 文件大小： | 185K |
| 代理商： | M30260M6A-XXXGP-D5 |
M16C/26A Group (M16C/26A, M16C/26T)
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
Rev.0.40 2004.07.30
page 14 of 24
REJ03B0071-0040Z
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
相关PDF资料 |
PDF描述 |
|---|---|
| M30260F3TGP-D3 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30263F3AFP-D5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO42 |
| M30260F6AGP-D5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260F8TGP-U3 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260F4AGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M30260T2-CPE-GP | 功能描述:DEV COMPACT EMULATOR M16C/26A,28 RoHS:否 类别:编程器，开发系统 >> 内电路编程器、仿真器以及调试器 系列:- 产品变化通告:Development Systems Discontinuation 19/Jul/2010 标准包装:1 系列:* 类型:* 适用于相关产品:* 所含物品:* |
| M30260T-EPB-GP | 制造商:Renesas Electronics Corporation 功能描述:DEV EMULATOR PERSONALITY KIT M16C/26 - Boxed Product (Development Kits) |
| M30262F3AGP#U5A | 制造商:Renesas Electronics Corporation 功能描述: |
| M30262F3GP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30262F3GP D3 | 制造商:Renesas Electronics Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。