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参数资料
型号： M30621FCAGP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80
封装： 14 X 14 MM, 0.65 MM PITCH, PLASTIC, QFP-80
文件页数： 23/143页
文件大小： 3168K
代理商： M30621FCAGP
UART2 Special Mode Register
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
116
P70/TxD2/SDA
P71/RxD2/SCL
CLK
control
P72/CLK2
Falling edge
detection
UART2 reception/ACK interrupt
request, DMA1 request
To DMA0, DMA1
To DMA0
2
P70 through P72 conforming to the simplified I C bus
I/O
Timer
UART2
Timer
UART2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1)
IICM=0
or IICM2=1
IICM=1
and IICM2=0
SDHI
Noize
Filter
Timer
UART2
I/O
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UART2
IICM=1
IICM=0
IICM=1
IICM=0
S
R
Q
IICM=1
IICM=0
I/O
R
Q
ALS
IICM=0 or
DL
≠000 (SDDS=1)
SDDS=0
or DL=000
SDDS=1 and
DL
≠000
SWC2
Falling edge of 9 bit
SWC
IICM=1
and IICM2=0
IICM=0
or IICM2=1
Selector
Noize
Filter
Noize
Filter
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 1 of the direction register.
Port reading
External clock
Internal clock
9th pulse
Bus collision
detection
Bus collision/start, stop condition
detection interrupt request
UART2 transmission/
NACK interrupt request
Start condition
detection
Stop condition
detection
L-synchronous
output enabling
bit
(Port P71 output data latch)
Data bus
Reception register
Bus busy
Transmission
register
Arbitration
Analog
delay
Digital delay
(Divider)
Note: P72/CLK2 is not connected to the outside.
Figure 1.14.26. Functional block diagram for I2C mode
Function
Normal mode
I2C mode (Note 1)
Factor of interrupt number 15 (Note 2)
UART2 transmission
No acknowledgment detection (NACK)
Factor of interrupt number 16 (Note 2)
UART2 reception
Start condition detection or stop
condition detection
UART2 transmission output delay
Not delayed
Delayed (digital or analog delay can be selected)
P70 at the time when UART2 is in use
TxD2 (output)
SDA (input/output) (Note 3)
P71 at the time when UART2 is in use
RxD2 (input)
SCL (input/output)
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
UART2 reception
Acknowledgment detection (ACK)
Noise filter width
15ns
50ns
Reading P71
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
1
2
3
4
5
6
7
8
9
Note 1: Make the settings given below when I2C mode is in use.
Set “0 1 0 2” in bits 2, 1, and 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
Factor of interrupt number 10 (Note 2)
Bus collision detection
Acknowledgment detection (ACK)
10 Initial value of UART2 output
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P70 when the port is
selected
Table 1.14.9. Features in I2C mode
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