Electrical Characteristics (Vcc1
≥ Vcc2 = 3V)
251
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC1
≥ VCC2 = 3V
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC, CM15=“1” unless otherwise
specified)
Figure 1.26.11
Table 1.26.46. Memory expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Symbol
Standard
Measuring condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address output delay time
50
ns
th(BCLK-AD)
Address output hold time (refers to BCLK)
4
ns
td(BCLK-CS)
Chip select output delay time
50
ns
th(BCLK-CS)
Chip select output hold time (refers to BCLK)
4
ns
th(RD-AD)
Address output hold time (refers to RD)
(Note 1)
td(BCLK-RD)
RD signal output delay time
40
ns
th(BCLK-RD)
RD signal output hold time
0
ns
th(WR-AD)
Address output hold time (refers to WR)
(Note 1)
td(BCLK-WR)
WR signal output delay time
40
ns
td(BCLK-DB)
Data output delay time (refers to BCLK)
50
ns
th(BCLK-DB)
Data output hold time (refers to BCLK)
4
ns
td(DB-WR)
Data output delay time (refers to WR)
(Note 2)
ns
td(BCLK-ALE)
ALE signal output delay time (refers to BCLK)
40
ns
th(BCLK-ALE)
ALE signal output hold time (refers to BCLK)
– 4
ns
th(ALE-AD)
ALE signal output hold time (refers to Adderss)
30
ns
th(BCLK-WR)
WR signal output hold time
0
ns
th(RD-CS)
Chip select output hold time (refers to RD)
th(WR-CS)
Chip select output hold time (refers to WR)
(Note 1)
ns
td(AD-RD)
RD signal output delay from the end of Address
ns
0
td(AD-WR)
WR signal output delay from the end of Address
ns
0
tdZ(RD-AD)
Address output floating start time
ns
8
th(WR-DB)
Data output hold time (refers to WR)
ns
(Note 1)
Note 1: Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
td(AD-ALE)
ALE signal output delay time (refers to Address)
ns
(Note 3)
Note 2: Calculated according to the BCLK frequency as follows:
f(BCLK)
(n–0.5) X 109
–50
[ns]
Note 3: Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
–40
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
(Note 1)