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| 型号： | M30624FGPGP-D9 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 55/87页 |
| 文件大小： | 919K |
| 代理商： | M30624FGPGP-D9 |
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VCC1 = VCC2 = 3V
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
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page 59
Table 5.46 Memory expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
Switching Characteristics
Symbol
Standard
Measuring
Condition
Max.
Min.
ParameterUnit
td(BCLK-AD)
Address Output Delay Time30ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)4
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)4
ns
td(BCLK-ALE)
ALE Signal Output Delay Time25ns
th(BCLK-ALE)
ALE Signal Output Hold Time
–4
ns
td(BCLK-RD)
RD Signal Output Delay Time30ns
th(BCLK-RD)
RD Signal Output Hold Time0
ns
td(BCLK-WR)
WR Signal Output Delay Time30ns
th(BCLK-WR)
WR Signal Output Hold Time0
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)40ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)(3)
4ns
th(WR-DB)
Data Output Hold Time (in relation to WR)(3)
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)ns
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
(n–0.5) X 109
– 40
[ns]
td(BCLK-CS)
Chip Select Output Delay Time30ns
th(RD-AD)
Address Output Hold Time (in relation to RD)0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
ns
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1k
, hold time
of output “L” level is
t = – 30pF X 1k
X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.
DBi
R
C
(NOTE 1)
(NOTE 2)
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
When n=1, f(BCLK) is 12.5MHz or less.
– 10
NOTES:
HLDA Output Delay Time
40ns
td(BCLK-HLDA)
See Figure 5.12
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相关代理商/技术参数 |
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| M30624MG-247FP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30624MG-327FP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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