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参数资料
型号： M30626FHPFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封装： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件页数： 31/104页
文件大小： 1313K
代理商： M30626FHPFP
M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
Rev.2.41
Jan 10, 2006
Page 30 of 96
REJ03B0001-0241
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Data Registers (1)
Address Registers (1)
Frame Base Registers (1)
Program Counter
Interrupt Table Register
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
Flag Register
NOTES:
1. These registers comprise a register bank. There are two register banks.
R0H
b15
b8 b7
b0
R3
INTBH
USP
ISP
SB
C
D
Z
S
B
O
I
U
IPL
R0L
R1H
R1L
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15
b0
PC
b19
b0
b15
b0
FLG
b15
b0
b15
b0
b7
b8
Reserved Area
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
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相关代理商/技术参数
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