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| 型号： | M30626FJPFP-D5 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 69/87页 |
| 文件大小： | 919K |
| 代理商： | M30626FJPFP-D5 |
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M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62PT)
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page 71
Table 5.49 Recommended Operating Conditions (1)
4.0
5.5
Typ.Max.
Unit
Parameter
VCC1, VCC2
5.0
Supply Voltage(VCC1=VCC2)
Symbol
Min.
Standard
Analog Supply Voltage
VCC1
AVcc
V
0
Analog Supply Voltage
Supply Voltage
VIH
IOH (avg)
HIGH Average
Output Current
mA
Vss
AVss
0.8VCC2
V
VCC2
0.2VCC2
0.2VCC1
0
LOW Input
Voltage
IOH (peak)
HIGH Peak Output
Current
HIGH Input
Voltage
-5.0
-10.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7
V
0.8VCC2
VCC2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)
LOW Peak Output
Current
10.0
5.0
mA
f (XIN)
Main Clock Input Oscillation Frequency
LOW Average
Output Current
IOL (peak)
mA
IOL (avg)
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P7_0 , P7_1
0.8VCC1
6.5
V
VIL
VCC1=4.0 to 5.5V
0MHz
16
f (XCIN)
Sub-Clock Oscillation Frequency
kHz
50
32.768
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
NOTES:
1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = -40 to 85
°C / -40 to 125 °C unless otherwise specified.
T version = -40 to 85
°C, V version = -40 to 125 °C.
2. The mean output current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL(peak)
for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2
must be -40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH(peak) for ports
P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1
must be -40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
0.8VCC1
V
VCC1
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
XIN, RESET, CNVSS, BYTE
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)
V
0.2VCC2
0
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
P11_0 to P11_7, P14_0, P14_1,
f (Ring)
On-chip Oscillation Frequency
MHz
1
f (PLL)
PLL Clock Oscillation Frequency (4)
VCC1=4.0 to 5.5V
10
MHz
24
f (BCLK)
CPU Operation Clock
0
MHz
24
tSU(PLL)
PLL Frequency Synthesizer Stabilization Wait TimeVCC1=5.0V20
ms
0.5
2
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