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参数资料
型号： M3062JFHTFP-U
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封装： 14 X 20 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, QFP-100
文件页数： 57/87页
文件大小： 919K
代理商： M3062JFHTFP-U
VCC1 = VCC2 = 3V
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
o
4
0
2
,
1
0
p
e
S
0
3
.
2
.
v
e
R
Z
0
3
2
0
-
1
0
B
3
0
J
E
R
page 60
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC, unless otherwise specified)
Table 5.47 Memory expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Symbol
Standard
Measuring
Condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address Output Delay Time
50
ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
4
ns
td(BCLK-CS)
Chip Select Output Delay Time
50
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
(NOTE 1)
td(BCLK-RD)
RD Signal Output Delay Time
40
ns
th(BCLK-RD)
RD Signal Output Hold Time
0
ns
th(WR-AD)
Address Output Hold Time (rin relation to WR)
(NOTE 1)
td(BCLK-WR)
WR Signal Output Delay Time
40
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
50
ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
4
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
(NOTE 2)
ns
th(BCLK-WR)
WR signal Output Hold Time
0
ns
th(RD-CS)
Chip Select Output Hold Time (in relation to RD)
th(WR-CS)
Chip Select Output Hold Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)
ns
(NOTE 1)
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
(n–0.5) X 109
–50
[ns]
3. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
–40
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
(NOTE 1)
td(BCLK-ALE)
ALE Signal Output Delay Time (in relation to BCLK)
25
ns
th(BCLK-ALE)
ALE Signal Output Hold Time (in relation to BCLK)
– 4ns
th(ALE-AD)
ALE Signal Output Hold Time (in relation to Adderss)
ns
td(AD-RD)
RD Signal Output Delay From the End of Address
ns
0
td(AD-WR)
WR Signal Output Delay From the End of Address
ns
0
tdZ(RD-AD)
Address Output Floating Start Time
ns
8
td(AD-ALE)
ALE Signal Output Delay Time (in relation to Address)
ns
(NOTE 3)
(NOTE 4)
–10
4. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
–15
[ns]
NOTES:
HLDA Output Delay Time
td(BCLK-HLDA)
40
ns
See Figure 5.12
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