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参数资料
| 型号： | M306H7MC-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 12/115页 |
| 文件大小： | 3146K |
| 代理商： | M306H7MC-XXXFP |
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Rev.2.10
Oct 25, 2006
Page 109 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.3
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Tables 10.5 lists the specifications of the UART mode.
Table 10.5
UART Mode Specifications
Item
Specification
Transfer data format
Character bit (transfer data): Selectable from 7, 8 or 9 bits
Start bit: 1 bit
Parity bit: Selectable from odd, even, or none
Stop bit: Selectable from 1 or 2 bits
Transfer clock
UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin.
n :Setting value of UiBRG register
0016 to FF16
Transmission, reception control
_______
_______ _______
Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition
Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_ If CTS function is selected, input on the CTSi pin = “L”
Reception start condition
Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection
For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
Framing error
This error occurs when the number of stop bits set is not detected
Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
Separate CTS/RTS pins (UART0)
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Interrupt request
generation timing
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