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参数资料
| 型号： | M306H7MG-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 3/115页 |
| 文件大小： | 3146K |
| 代理商： | M306H7MG-XXXFP |
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Rev.2.10
Oct 25, 2006
Page 100 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.7
U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
UARTi special mode register 2 (i=0 to 2)
Symbol
Address
After reset
U0SMR2 to U2SMR2 036E16, 037216, 037616
X00000002
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
RW
Function
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit
0 : Disabled
1 : Enabled
SDA output stop bit
UARTi initialization bit
Clock-synchronous bit
Refer to Table 10.12
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS
0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: Transfer clock
1: “L” output
2
UARTi special mode register 3 (i=0 to 2)
Symbol
Address
After reset
U0SMR3 to U2SMR3
036D16, 037116, 037516
000X0X0X2
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
Function
DL2
SDAi digital delay
setup bit
(Note 1, Note 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
b7 b6 b5
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output select bit
CKPH
NODC
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
RW
(b7)
RW
(b0)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
(b4)
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