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参数资料
| 型号： | M30828MH-XXXGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件页数： | 8/48页 |
| 文件大小： | 847K |
| 代理商： | M30828MH-XXXGP |
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Note 6:
To guarantee accuracy, it is required that V
A and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 7:
Typical figures are at T
A = 25°C, and represent most likely parametric norms. Test limits are guaranteed to MIL-PRF-38535.
Note 8:
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 9:
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 10:
This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 11:
The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 12:
Each of the two converters of the ADC08D1520 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each
bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the
first bus (Dd0 through Dd7). 1:2 Demux Mode.
Note 13:
Tying V
BG to the supply rail will increase the output offset voltage (VOS) by 300mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (V
OD), causing it to increase by 30mV (typical).
Note 14:
Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in MIL-STD-883, Method 1019
Specification Definitions
APERTURE (SAMPLING) DELAY
is the amount of delay,
measured from the sampling edge of the Clock input, after
which the signal present at the input pin is sampled inside the
device.
APERTURE JITTER (t
AJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
CODE ERROR RATE (C.E.R.)
is the probability of error and
is defined as the probable number of word errors on the ADC
output per unit of time divided by the number of words seen
in that amount of time.. A C.E.R. of 10-18 corresponds to a
statistical error in one word about every four (4) years.
CLOCK DUTY CYCLE
is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
DIFFERENTIAL NON-LINEARITY (DNL)
is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at sample rate = 500 MSPS with a 1MHz input
sinewave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS)
is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW)
is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full-scale input.
GAIN ERROR
is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
Positive Gain Error = Offset Error Positive Full-Scale
Error
Negative Gain Error = (Offset Error Negative Full-
Scale Error)
Gain Error = Negative Full-Scale Error Positive Full-
Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL)
is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value. The best fit method is used.
INTERMODULATION DISTORTION (IMD)
is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT)
is the bit that has the small-
est value or weight of all bits. This value is
V
FS / 2
N
where V
FS is the differential full-scale amplitude VIN as set by
the FSR input and "N" is the ADC resolution in bits, which is
8, for the ADC08D1520.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
DIFFERENTIAL OUTPUT VOLTAGE (V
OD) is the absolute
value of the difference between the V
D+ and VD- outputs; each
measured with respect to Ground.
www.national.com
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ADC08D1520QML
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