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参数资料
| 型号： | M312L5720BG0-A2 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Registered Module |
| 中文描述： | DDR SDRAM的注册模块 |
| 文件页数： | 11/18页 |
| 文件大小： | 274K |
| 代理商： | M312L5720BG0-A2 |
DDR SDRAM
1GB, 2GB Registered DIMM
Rev. 1.1 August. 2003
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25
°
C, f=1MHz)
Parameter
Symbol
M312L2920BG0
Unit
Min
9
9
9
11
10
10
10
Max
11
11
11
12
11
11
11
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Parameter
Symbol
M312L2923BG0, M312L5720BG0
Min
9
9
9
11
13
13
13
Unit
Max
11
11
11
12
15
15
15
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
V
REF
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| M312L5720BG0-B0 | DDR SDRAM Registered Module |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M312L5720BG0-B0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Registered Module |
| M312L5720BG0-CB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Registered Module |
| M312L5720CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512 DDR SDRAM MODUL X72 BOC(LF) - Trays |
| M312L6420ETS | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Registered Module |
| M312L6420HUS | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Product Guide |
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