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参数资料
| 型号： | M32000D3FP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 24/155页 |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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1-4
OVERVIEW
M32000D3FP User's Manual
1.1 Performance overview
1.1.4 Internal clock multiplier circuit
The M32000D3FP internally multiplies the frequency of the input clock signal by four. When the internal
operating frequency is 66.6 MHz, the input clock frequency is 16.65 MHz.
1.1.5 Internal memory controller
(1) Cache modes for internal DRAM and external program ROM
The M32000D3FP has an internal 4 KB cache memory. The memory controller supports the following
3 modes.
(a) internal instruction/data cache mode
(b) instruction cache mode
(c) cache-off mode
The internal instruction/data cache mode uses the internal DRAM as main memory. The 4 KB cache
memory operates in this case as a direct map cache memory for instructions and data stored in the
internal DRAM. Writing is carried out by the copy back method, so that data traffic between cache
memory and the internal DRAM is kept to a minimum.
The instruction cache mode uses an external ROM as the program memory and the internal DRAM
as data memory. The 4 KB cache memory operates in this case as a direct map cache memory for
all instructions stored in the user’s memory space. Caching of data is not performed.
(2) Flexible DRAM control
The internal DRAM is automatically refreshed by the internal memory controller.
The internal DRAM can also be accessed by external devices. In this case, the internal DRAM can
be used as normal memory.
1.1.6 Master/slave mode
The M32000D3FP has a slave mode additional to its master mode. When set to slave mode, the M32000D3FP
can be used as a coprocessor without it accessing the external bus immediately after the reset.
1.1.7 Power management function
The M32000D3FP has a standby mode and a CPU sleep mode to manage power this is in consideration
of portable equipment applications.
When set to standby mode by the internal memory controller, all clock supplies are stopped. However,
in this case, the internal DRAM refreshes itself using a free running timer.
When set to CPU sleep mode by the memory controller, only the clock supply to the M32000D3FP CPU
is stopped. In this case, the internal DRAM can be accessed by external devices because the internal
DRAM and cache are operating.
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