
9
DMAC
9-31
32180 Group User’s Manual (Rev.1.0)
9.3 Functional Description of the DMAC
Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7
REQSL7
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
Software start
When any data is written to the DMA7 Software Request Generation Register
0
1
Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty
1
0
MJT (TIN2 input signal)
When MJT TIN2 input signal is generated
1
Extended DMA7 transfer request
The source selected by the DMA7 Channel Control Register 1 (DM7CNT1)
source selected
REQESEL7 bits (see below)
REQESEL7 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA6 transfer completed
When one DMA6 transfer is completed (cascade mode)
0001
MJT (TOU0_2irq)
MJT TOU0_2 interrupt source
0010
Serial I/O3 (reception completed)
When serial I/O3 reception is completed
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8
REQSL8
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
Software start
When any data is written to the DMA8 Software Request Generation Register
0
1
MJT (input event bus 0)
When MJT input event bus 0 signal is generated
1
0
Serial I/O3 (reception completed)
When serial I/O3 reception is completed
1
Extended DMA8 transfer request
The source selected by the DMA8 Channel Control Register 1 (DM8CNT1)
source selected
REQESEL8 bits (see below)
REQESEL8 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
MJT (TIN7 input signal)
When MJT TIN7 input signal is generated
0001
MJT (TOU0_6irq)
MJT TOU0_6 interrupt source
0010
One DMA7 transfer completed
When one DMA7 transfer is completed (cascade mode)
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111