
NON-BREAK DEBUG (NBD)
16
16-8
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
Output
Input
NBDCLK
NBDSYNC#
0001
Ready
NBDD3 NBDD0
Not Ready
Ready
Note 1: When input adress from NBDD0 - NBDD3 is completed, plug sence packet is outputted though high impedance period of 1NBDCLK.
Note 2: After "H" level detection by rising NBDCLK, read out data (read data packet)is outputted from next NBDCLK rising.
Note:
:Sampling point
0000
SIZ1, SIZ0,
R/W, I/T
A0 A3
Hi-Z
D28 D31
D0 D3
A28 A31
Hi-Z
0000
0001
(Note 1)
(Note 2)
Figure 16.5.2 Example of Write Operation (for 32-Bit Write to the CPU Space)
16.5 RAM Monitor Function
16.5.1 Description of NBD Operation
Figure 16.5.1 shows an example of read operation of the NBD. Figure 16.5.2 shows an example of write
operation of the NBD. When input to the NBDSYNC# pin is pulled "L," the NBD starts taking in a command
packet from NBDD3–NBDD0 in the format shown in Figure 16.4.1. When the command packet input finishes,
the NBD starts reading/writing to or from the address specified in the address field. When the NBD finishes
receiving a command packet, it starts outputting data from NBDD3–NBDD0 in the format shown in Figure
16.4.2 after the data bus is temporarily placed in the high-impedance (Hi-Z) state for 1 NBDCLK cycle. While
input to the NBDSYNC# pin is held "L," NBDD3–NBDD0 are in a flag sense state, in which they output Not
Ready (0000) during a read/write operation or Ready (0001) when the operation has finished.
During a read, when input to the NBDSYNC# pin is released back "H" after detecting Ready, the read data
(read data packet) is output (Figure 16.5.1).
Before a next command packet can be transmitted, input to the NBDSYNC# pin must be held "H" for at least 2
NBDCLK cycles.
Output
Input
NBDCLK
NBDSYNC#
NBDD3 NBDD0
0001
Ready
Not Ready
Ready
(Note 2)
(Note 1)
Hi-Z
0000
SIZ1, SIZ0,
R/W, I/T
Hi-Z
A28 A31
A0 A3
Hi-Z
0000
0001
D4 D7
D0 D3
0001
Note 1: When input adress from NBDD0 - NBDD3 is completed, plug sence packet is outputted though high impedance period of 1NBDCLK.
Note 2: After "H" level detection by rising NBDCLK, read out data (read data packet)is outputted from next NBDCLK rising.
Note:
:Sampling point
Figure 16.5.1 Example of Read Operation (for 8-Bit Read from the CPU Space)
16.5 RAM Monitor Function