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参数资料
| 型号： | M34283G2-XXXGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件页数： | 15/41页 |
| 文件大小： | 441K |
| 代理商： | M34283G2-XXXGP |
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Rev.1.01
Mar 20, 2006
page 20 of 62
REJ03B0109-0101
4283 Group
RAM BACK-UP MODE
The 4283 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the functions and states of
reset circuit at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 24 shows
the state transition.
(1) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
(2) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
reset by power-on reset circuit is performed
reset by watchdog timer is performed
reset by voltage drop detection circuit is performed
In this case, the P flag is “0.”
(3) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
Table 7 Functions and states retained at RAM back-up
RAM back-up
O
O
O
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port CARR
Ports D0–D7
Ports E0, E1
Port G
Timer control registers V1, V2
Pull-down control registers PU0, PU1
Logic operation selection register LO
Timer 1 function, Timer 2 function
Timer underflow flags (T1F, T2F)
Watchdog timer (WDT)
Watchdog timer flags (WDF1, WDF2)
Most significant ROM code reference enable
flag (URS)
Notes 1: “O” represents that the function can be retained, and
“” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “112” at RAM back-up.
Fig. 24 State transition
Fig. 25 Set source and clear source of the P flag
Fig. 26 Start condition identified example using the SNZP
instruction
: Microcomputer starts its operation after f(XIN) is counted to16384 times.
Stabilizing time a
POF instruction
is executed
A
f(XIN) oscillation
Return input
B
(RAM back-up
mode)
f(XIN) stop
Reset
(Stabilizing time a )
S
R
Q
Power down flag P
POF instruction
Reset input
● Set source
POF instruction is executed
● Clear source
Reset input
Software start
P = “1”
?
Yes
Warm start
Cold start
No
相关PDF资料 |
PDF描述 |
|---|---|
| M34502E4FP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO24 |
| M34502M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34502M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34508G4GP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| M34508G4H-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M34286 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34286G2GP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34286G2GP#U0 | 功能描述:MCU 1.8/3.6V 2KB ROM 20-LSSOP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:720/4500 标准包装:38 系列:Encore!® XP® 核心处理器:eZ8 芯体尺寸:8-位 速度:5MHz 连通性:IrDA，UART/USART 外围设备:欠压检测/复位，LED，POR，PWM，WDT 输入/输出数:16 程序存储器容量:4KB（4K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:1K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 3.6 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 105°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:管件 其它名称:269-4116Z8F0413SH005EG-ND |
| M34286G2GP#WC | 制造商:Renesas Electronics Corporation 功能描述:4BIT MCU |
| M34286G2-XXXGP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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