参数资料
型号: M34508G4FP
元件分类: 微控制器/微处理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20
封装: 5.30 X12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件页数: 6/106页
文件大小: 1059K
代理商: M34508G4FP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
4508 Group
Rev.1.03
2009.07.27
page 101 of 140
REJ03B0148-0103
TADAB (Transfer data to register AD from Accumulator from register B)
1000111001
239
11
Grouping:
A/D conversion operation
Description: In the comparator mode (Q13 = 1), transfers
the contents of register B to the high-order 4
bits (AD7–AD4) of comparator register, and
the contents of register A to the low-order 4
bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this in-
struction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
Operation:
Q13 = 1: (AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 0: TADAB = NOP
TAI1 (Transfer data to Accumulator from register I1)
1001010011
253
11
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
Operation:
(A) ← (I1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAD (Transfer data to Accumulator from register D)
0001010001
051
11
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation:
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TABSI (Transfer data to Accumulator and register B from register SI)
1001111000
278
11
Grouping:
Serial interface operation
Description: Transfers the high-order 4 bits of serial inter-
face register SI to register B, and transfers
the low-order 4 bits of serial interface regis-
ter SI to register A.
Operation:
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
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