参数资料
型号: M34518M4-XXXSP
元件分类: 微控制器/微处理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
封装: 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件页数: 10/160页
文件大小: 1078K
代理商: M34518M4-XXXSP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.3.01
2005.06.15
page 107 of 157
REJ03B0008-0301
4518 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag)
0000101111
02F
11
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the con-
tents of carry flag CY is “0.”
After skipping, the CY flag remains un-
changed.
Executes the next instruction when the con-
tents of the CY flag is “1.“
Operation:
(CY) = 0 ?
SZD (Skip if Zero, port D specified by register Y)
0000100100
024
22
(D(Y)) = 0
(Y) = 0 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
1000110000
230
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 re-
load register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
Operation:
(T17–T14)
← (B)
(R17–R14)
← (B)
(T13–T10)
← (A)
(R13–R10)
← (A)
Operation:
(D(Y)) = 0 ?
(Y) = 0 to 7
2
16
0000101011
02B
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
1000110001
231
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
Operation:
(T27–T24)
← (B)
(R27–R24)
← (B)
(T23–T20)
← (A)
(R23–R20)
← (A)
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