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参数资料
| 型号： | M34D64-W |
| 厂商： | 意法半导体 |
| 元件分类： | DRAM |
| 英文描述： | 64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| 中文描述： | 64千位串行I2C总线的EEPROM，带有硬件写控制记忆的热门季 |
| 文件页数： | 2/21页 |
| 文件大小： | 147K |
| 代理商： | M34D64-W |
M34D64
2/21
SUMMARY DESCRIPTION
These
I
2
C-compatible
programmable memory (EEPROM) devices are
organized as 8192 x 8.
electrically
erasable
Figure 2. Logic Diagram
These devices are compatible with the I
2
C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I
2
C
bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 1. Signal Names
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
Figure 3. SO and TSSOP Connections
Note: 1. See page 17 (onwards) for package dimensions, and how
to identify pin-1.
AI02850B
3
E0-E2
SDA
VCC
M34D64
WC
SCL
VSS
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDA
VSS
SCL
WC
E1
E2
E0
VCC
AI02851C
M34D64
1
2
3
4
8
7
6
5
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M34D64-W_08 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit serial IC bus EEPROM with hardware write control on top quarter of memory |
| M34D64-WBN6 | 功能描述:电可擦除可编程只读存储器 5.5V 64K (8192x8) RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| M34D64WBNT1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64WBNT5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64WBNT6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
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