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参数资料
| 型号： | M35502AFP |
| 元件分类： | 显示控制器 |
| 英文描述： | 7 X 18 SEGMENTS FLUORESCENT DSPL CTRL, PDSO36 |
| 封装： | 0.450 INCH, PLASTIC, SSOP-36 |
| 文件页数： | 16/16页 |
| 文件大小： | 218K |
| 代理商： | M35502AFP |
9
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
CLOCK GENERATING CIRCUIT
Oscillating circuit is built up by connecting a capacitor between pins
OSC and VSS.
When supplying a clock externally, input it to the OSC pin.
Fig.10 CR generating circuit
Fig.11 External clock input circuit
HANDLING OF UNUSED PINS
Handle unused pins as the follow.
Pin
Segment
Digit
Analog input
Handling
Open
Connect to VCC or VSS through a resistor.
Table 2 Handling of unused pins
POWER-ON RESET
Reset can be performed automatically during power on (power-on reset) by the built-in power-on reset circuit.
Fig.12 Power-on reset
OSC
COSC
OSC
VCC
VSS
External oscillation circuit
VDD
Reset state
Internal reset signal
Reset released
Poweron
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