参数资料
型号: M37270EFSP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP64
封装: 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件页数: 37/94页
文件大小: 1551K
代理商: M37270EFSP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
42
Fig. 45. START condition/STOP condition detecting timing
diagram
(8) START/STOP Condition Detecting Condi-
tions
The START/STOP condition detecting conditions are shown in Fig-
ure 45 and Table 9. Only when the 3 conditions of Table 9 are satis-
fied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” occurs to the
CPU.
(9) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I2C address register (address
00F716). At the time of this comparison, address comparison of
the RBW bit of the I2C address register (address 00F716) is not
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 46, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I2C address
register (address 00F716). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I2C address regis-
ter (address 00F716) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
Hold time
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Hold time
Setup
time
Standard clock mode
6.5
s (26 cycles) < SCL
release time
3.25
s (13 cycles) < Setup time
3.25
s (13 cycles) < Hold time
Table 9. START condition/STOP condition detecting conditions
Note: Absolute time at
φ = 4 MHz. The value in parentheses de-
notes the number of
φ cycles.
Fig. 46. Address data communication format
S
Slave address
A
Data
A
Data
A/A
P
R/W
7 bits
“0”
1 to 8 bits
S
Slave address
A
Data
A
Data
AP
7 bits
“1”
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
1st 7 bits
A
Data
7 bits
“0”
8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
2nd byte
A
Data
A/A
P
1 to 8 bits
S
Slave address
1st 7 bits
A
7 bits
“0”
8 bits
7 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd byte
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
AP
1 to 8 bits
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
P : STOP condition
A : ACK bit
R/W : Read/Write bit
Sr : Restart condition
From master to slave
From slave to master
R/W
High-speed clock mode
1.0
s (4 cycles) < SCL
release time
0.5
s (2 cycles) < Setup time
0.5
s (2 cycles) < Hold time
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