参数资料
型号: M3727GM6-XXXFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
封装: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数: 57/131页
文件大小: 1130K
代理商: M3727GM6-XXXFP
M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Rev.1.00
Apr 01, 2001
page 29 of 127
REJ03B0132-0100Z
8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register. Reading data from the I2C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I C data shift register1(S0) [Address 00F616]
B
Functions
After reset
R W
I C Data Shift Register
0
to
7
This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
Note:
2
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Name
D0 to D7
R W
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