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| 型号： | M3727GM8-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件页数： | 62/129页 |
| 文件大小： | 1357K |
| 代理商： | M3727GM8-XXXSP |
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M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Rev.1.00
Apr 01, 2001
page 38 of 127
REJ03B0132-0100Z
8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00FA16).
Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00F616) and set
“0” in the least significant bit.
Set “F016” in the I2C status register (address 00F816) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I2C data shift register (address 00F616). At
this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step .
Set “D016” in the I2C status register (address 00F816). After this, if
ACK is not returned or transmission ends, a STOP condition will
be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in
the I2C clock control register (address 00FA16).
Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
When a START condition is received, an address comparison is
made.
When all transmitted address are“0” (general call):
AD0 of the I2C status register (address 00F816) is set to “1”and
an interrupt request signal occurs.
When the transmitted addresses match the address set in :
ASS of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above:
AD0 and AAS of the I2C status register (address 00F816) are set
to “0” and no interrupt request signal occurs.
Set dummy data in the I2C data shift register (address 00F616).
When receiving control data of more than 1 byte, repeat step .
When a STOP condition is detected, the communication ends.
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