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HARDWARE
1-113
7470/7471/7477/7478 GROUP USER’S MANUAL
1.13 Serial I/O
[Clock synchronous Serial I/O receive setting method]
1Clear the Serial I/O receive interrupt enable bit (bit 5 of interrupt control register 1) to “0.”
2When selecting the internal clock, set the BRG value.
3Set the Serial I/O control register according to Table 1.13B.2.
4When using a Serial I/O receive interrupt
[1] Clear the Serial I/O receive interrupt request bit (bit 5 of interrupt request register 1) to “0.”
Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive
interrupt request bit may be set. Clear the Serial I/O receive interrupt request bit to “0”
after one instruction or more after switching the ordinary port over to the Serial I/O port.
[2] Set the Serial I/O receive interrupt enable bit to “1.”
5Set the following data into the Transmit buffer register (TB).
Transmit data in the full-duplex data communication
Arbitrary dummy data in the half-duplex data communication
Note: When the external clock is selected, perform a write operation while the synchronous
clock is at “H.”
Table 1.13B.2 Clock synchronous Serial I/O receive setting
Item
Serial I/O control register
(SIOCON: Address 00E216)
Bit
Setting value
Register to be used
Receive enable selection
Clock synchronous selection
Serial I/O enable selection
f(XIN)/4
f(XIN)/16
BRG output divided by 4
External clock input
Ordinary port
__________
SRDY
signal output (Note 2)
Disable (half-duplex data communication)
Enable (full-duplex data communication)
Receive enable
Clock synchronous
P14 to P17 function as Serial I/O pins
Notes 1: f(XCIN)/4 (setting value : 0), f(XCIN)/16 (setting value : 1) can be selected in the 7478
Group.
2:
__________
When the receive side performs an SRDY output by using an external clock, set the
__________
receive enable bit, the SRDY output enable bit, and the transmit enable bit to “1”
(transmit enable).
3: When the external clock is selected, write “1” in bit 4 (transmit enable bit) while the
synchronous clock is at “H.”
b0
b1
b2
b4
b5
b6
b7
0
1
0
1
0
1
0
1(Note 3)
1
BRG count source selection
(Note 1)
Synchronous clock selection
__________
SRDY
signal output selection
Transmit enable selection