HARDWARE
1-94
7470/7471/7477/7478 GROUP USER’S MANUAL
1.13 Serial I/O
[Transmit setting method]
1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.”
2Set the Serial I/O mode register according to “Table 1.13A.1.”
3When using the Serial I/O interrupt,
[1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.”
[2] Set the Serial I/O interrupt enable bit to “1.”
4Write transmit data into the Serial I/O register (address 00DD16).
Note: When the external clock is selected, perform a write operation while the synchronous clock is
at “H.”
Table 1.13A.1 shows a Serial I/O transmit setting.
Table 1.13A.1 Serial I/O transmit setting
Serial I/O mode register
(SM: Address 00DC16)
Bit
Setting value
Serial I/O port using
Serial I/O
Byte specification mode selection
____________________
P15/SOUT, SRDY pin output
format
(Note 3)
External clock
Internal clock
Serial I/O port (SOUT, CLK) (Note 2)
Ordinary port
_______________
SRDY
signal output
_______________
SRDY
signal
SARDY signal
Ordinary mode
Byte specification mode
CMOS output
N channel open drain output
Item
Register to be used
Synchronous clock selection
____________________
SRDY
signal output selection
____________________
SRDY
signal selection
Synchronous clock (at internal
clock selection)
(Note 1)
Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group,
however, f(XCIN) is not available.
q When a divided signal of f(XIN) is selected, the system clock is f(XIN).
q When a divided signal of f(XCIN) is selected, the system clock is f(XCIN).
Select a system clock state by bit 7 of the CPU mode register.
2: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit
may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more
after switching the ordinary port over to the Serial I/O port.
3: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is
provided regardless of the set value of bit 7.
f(XIN)/8
f(XCIN)/8
f(XIN)/16
f(XCIN)/16
f(XIN)/32
f(XCIN)/32
f(XIN)/512
f(XCIN)/512
b1 b0
b2
b3
b4
b5
b6
b7
00
01
10
11
0
1
0
1
0
1
0
1
0
1