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参数资料
| 型号： | M37531M8-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36 |
| 封装： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件页数： | 3/216页 |
| 文件大小： | 1400K |
| 代理商： | M37531M8-XXXFP |
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4
4-5
EIT
32182 Group User’s Manual (Rev.1.0)
4.2 EIT Events
5) Invalid Operation Exception (IVLD)
The exception occurs when an invalid operation is executed. The following table shows the operation
results and the respective conditions in which each IVLD occurs.
Table 4.2.6 Operation Results When an IVLD Occurred
Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0"
Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1"
Note: NaN (Not a Number)
SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the
source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used
as the initial value in a variable. However, SNaNs cannot be generated by hardware.
QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the
source operand in an operation, an IVLD will not occur (excluding comparison and format conversion).
Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without
executing an EIT processing. QNaNs are created by hardware.
6) Unimplemented Exception (UIPL)
The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and
a denormalized number is given as an operation operand. (Note 1)
Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination
register remains unchanged.
Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if
the DN bit (FPSR register bit 23) = "0", an UIPL occurs.
4.2.2 Interrupt
(1) Reset Interrupt (RI)
Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the
highest priority.
For details about the reset interrupt, see Chapter 7, “Reset.”
(2) System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt
processing, control will not return to the program that was being executed when the interrupt occurred.
(3) External Interrupt (EI)
External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The
interrupt controller manages these interrupts by assigning each one of eight priority levels including an
interrupt-disabled state.
When an integer conversion
overflow ed
When FTOI
instruction
w as executed
When NaN or Infinity w as converted
into an integer
When FTOS
instruction
w as executed
Occurrence Condition
Operation for SNaN operand
+Infinity-(+Infinity), -Infinity-(-Infinity)
0 x Infinity
0 / 0, Infinity / Infinity
When < or > comparison w as performed on NaN
Operation Result (Content of the Destination Register)
When the IVLD EIT processing is masked (Note 1)
When the IVLD EIT
processing is executed
(Note 2)
Return value w hen pre-conversion signed bit is:
"0": H’7FFF FFFF
"1": H’8000 0000
Return value w hen pre-conversion signed bit is:
"0": H’0000 7FFF
"1": H’FFFF 8000
Comparison results (comparison invalid)
QNaN
No change
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M37531RSS | 制造商:Mitsubishi Electric 功能描述: |
| M37531T-ADS | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Temporary Target Board |
| M37532E8FP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37532M4 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37532M4-A17GP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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