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| 型号： | M37546G4SP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件页数： | 103/105页 |
| 文件大小： | 1105K |
| 代理商： | M37546G4SP |
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REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 95 of 100
7546 Group
3. Interrupt discrimination bit
Use an LDM instruction to clear to “0” an interrupt discrimination
bit.
LDM #%0000XXXX, $0B
Set the following values to “X”
“0”: an interrupt discrimination bit to clear
“1”: other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is cleared;
LDM #%00001110 and $0B.
4. Interrupt discrimination bit and interrupt request bit
For key-on wakeup, UART1 bus collision detection, A/D conver-
sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt
source set register (address 000A16)) is set “0: Invalid”, each inter-
rupt discrimination bit (interrupt source discrimination register
(address 000B16)) is set to “1: interrupt occurs” when correspond-
ing interrupt request occurs.
But corresponding interrupt request bit (interrupt request registers
1, 2 (addresses 003C16, 003D16) is not affected.
Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
2. When a count source of timer X, timer A or timer B is switched,
stop a count of the timer.
Notes on Timer X
1. CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit (bit 2 of timer X mode register (address 002B16)).
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
2. Timer X count source selection
The f(XIN) (frequency not divided) can be selected by the timer X
count source selection bits (bits 1 and 0 of timer count source set
register (address 002A16)) only when the ceramic oscillation or the
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
3. Pulse output mode
Set the direction register of port P14, which is also used as CNTR0
pin, to output.
When the TXOUT pin is used, set the direction register of port P03,
which is also used as TXOUT pin, to output.
4. Pulse width measurement mode
Set the direction register of port P14, which is also used as CNTR0
pin, to input.
Notes on Timer A, B
1. Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit (bit 0 (bit 2) of timer X mode register (address 001D16)), written
data to timer register is set to only latch even if timer is stopped or
operating. Accordingly, in order to set the initial value for timer
when it is stopped, set “0: Write to latch and timer simultaneously”
to timer A (B) write control bit.
2. Read/write of timer A
Stop timer A to read/write its data in the following state;
XIN oscillation selected by clock division ratio selection bits (bits 7
and 6 of CPU mode register (address 003B16)), and the on-chip
oscillator output is selected as the timer A count source.
3. Read/write of timer B
Stop timer B to read/write its data in the following state;
XIN oscillation selected by clock division ratio selection bits, the
timer A underflow is selected as the timer B count source, and the
on-chip oscillator output is selected as the timer A count source.
Notes on Output Compare
1. When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
2. Do not write the same data to both of compare latch x0 (x=0, 1,
2, 3) and x1.
3. When setting value of the compare register is larger than timer
setting value, compare match signal is not generated. Accord-
ingly, the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare register is
smaller than timer setting value, this compare match signal is
generated. Accordingly, if the corresponding compare latch y
(y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid), compare match interrupt request occurs.
4. When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled. Accordingly, the output waveform can be fixed to “L”
or “H” level.
However, in this case, the compare match signal is generated.
Accordingly, if the corresponding compare latch y (y=00, 01, 10,
11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid),compare match interrupt request occurs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M37546G4SP#U0 | 功能描述:MCU 2/5V 16KB 32-SDIP QZ-ROM RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 标准包装:250 系列:80C 核心处理器:8051 芯体尺寸:8-位 速度:16MHz 连通性:EBI/EMI，I²C，UART/USART 外围设备:POR，PWM，WDT 输入/输出数:40 程序存储器容量:- 程序存储器类型:ROMless EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-LCC（J 形引线） 包装:带卷 (TR) |
| M37546G4-XXXGP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37546G4-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37546G4-XXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37547G2FP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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