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参数资料
| 型号： | M38067MCAXXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 37/60页 |
| 文件大小： | 712K |
| 代理商： | M38067MCAXXXFP |
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39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
_____
Before
φ ONW input set up time
_____
After
φ ONW input hold time
Before
φ data bus set up time
After
φ data bus hold time
___ _____
Before RD ONW input set up time
___ _____
Before WR ONW input set up time
___ _____
After RD ONW input hold time
___ _____
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
____
tsu(ONW–
φ)
____
th(
φ–ONW)
tsu(DB–
φ)
th(
φ–DB)
____ __
tsu(ONW–RD)
____ ___
tsu(ONW–WR)
__
____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Symbol
Parameter
Limits
Min.
ns
Unit
–20
60
0
–20
65
0
Typ.
Max.
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After
φ AD15–AD8 delay time
After
φ AD15–AD8 valid time
After
φ AD7–AD0 delay time
After
φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
___
RD and WR delay time
___
RD and WR valid time
After
φ data bus delay time
After
φ data bus valid time
___
RD pulse width, WR pulse width
___
RD pulse width, WR pulse width
(When one-wait is valid)
___
After AD15–AD8 RD delay time
___
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
After AD7–AD0 WR delay time
___
After RD AD15–AD8 valid time
___
After WR AD15–AD8 valid time
___
After RD AD7–AD0 valid time
___
After WR AD7–AD0 valid time
___
After WR data bus delay time
___
After WR data bus valid time
_________
RESETOUT output delay time (Note 1)
_________
RESETOUT output valid time (Note 1)
40
45
20
10
70
65
200
Symbol
Parameter
Limits
Min.
ns
Unit
tc(XIN)–10
6
3
15
tc(XIN)–10
3tc(XIN)–10
tc(XIN)–35
tc(XIN)–40
0
10
0
2tc(XIN)
20
10
25
10
20
10
5
20
tc(XIN)–15
tc(XIN)–20
5
15
Typ.
Max.
tc(
φ)
twH(
φ)
twL(
φ)
td(
φ–AH)
tv(
φ–AH)
td(
φ–AL)
tv(
φ–AL)
td(
φ–SYNC)
tv(
φ–SYNC)
___
td(
φ–WR)
___
tv(
φ–WR)
td(
φ–DB)
tv(
φ–DB)
__
twL(RD)
___
twL(WR)
__
td(AH–RD)
___
td(AH–WR)
__
td(AL–RD)
___
td(AL–WR)
__
tv(RD–AH)
___
tv(WR–AH)
__
tv(RD–AL)
___
tv(WR–AL)
___
td(WR–DB)
___
tv(WR–DB)
___ _____
td(RESET–RESETOUT)
_____
tv(
φ–RESET)
Test conditions
Note 1:
__________
The RESETOUT output goes “H” in sync with the fall of the
φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
Fig. 32
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
3806 Group
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