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参数资料
| 型号： | M38207M8-XXXHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 0.50 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 54/69页 |
| 文件大小： | 944K |
| 代理商： | M38207M8-XXXHP |
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Rev.4.01
Nov 14, 2003
page 58 of 136
3803/3804 Group
Serial I/O3
Serial I/O3 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O3 mode can be selected by setting
the serial I/O3 mode selection bit of the serial I/O3 control register
(bit 6 of address 003216) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 48 Block diagram of clock synchronous serial I/O3
Fig. 49 Operation of clock synchronous serial I/O3
1/4
F/F
P36/SCLK3
Serial I/O3 status register
Serial I/O3 control register
P37/SRDY3
P34/RXD3
P35/TXD3
Receive buffer register 3
Address 003016
Receive shift register 3
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O3 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 3
Address 002F16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register 3
Data bus
Address 003016
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 003116
Data bus
Address 003216
Transmit shift register 3
f(XIN)
(f(XCIN) in low-speed mode)
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD3
Serial input RxD3
Write pulse to receive/transmit
buffer register (address 003016)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY3
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