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参数资料
| 型号： | M38503M2A-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-42 |
| 文件页数： | 44/99页 |
| 文件大小： | 1419K |
| 代理商： | M38503M2A-XXXSP |
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49
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 54 Structure of MISRG
[MISRG (MISRG)] 003816
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to “1”, XIN oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
3850 Group (Spec. H/A)
MISRG
(MISRG : address 003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
b7
b0
Note:When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16)
changes.
Not used (return “0” when read)
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
WIT instruction
STP instruction
Timing
φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
XIN
XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
1/2
Port XC
switch bit
“1”
“0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: When bit 0 of MISRG = “0”
Main clock division ratio
selection bits (Note 1)
FF16
0116
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Reset
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