参数资料
型号: M38748EDD-XXXGP
厂商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 单芯片8位CMOS微机
文件页数: 57/92页
文件大小: 1292K
代理商: M38748EDD-XXXGP
57
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
[A-D/D-A Conversion Register (AD)] 0035
16
The A-D/D-A conversion register is a register (at reading) that con-
tains the result of an A-D conversion. When reading this register
during an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D/D-A conversion process.
Bits 0 to 2 of this register select specific analog input pins. Bit 3
signals the completion of an A-D conversion. The value of this bit
remains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed. Writing “0” to this bit starts the
A-D conversion. When bit 5, which is the AD external trigger valid
bit, is set to “1”, this bit enables A-D conversion even by a falling
edge of an ADT input. Set “0” (input port) to the direction register
corresponding the ADT pin. Bit 6 is the interrupt source selection
bit. Writing “0” to this bit, A-D converter interrupt request occurs at
completion of A-D conversion. Writing “1” to this bit the interrupt
request occurs at falling edge of an ADT input.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P6
7
/AN
7
to
P6
0
/AN
0
and inputs it to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D/
D-A conversion register. When an A-D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
Fig. 60 Block diagram of A-D converter
Note that the comparator is constructed linked to a capacitor, so
set f(X
IN
) to at least 500 kHz during A-D conversion. Use a CPU
system clock dividing the main clock X
IN
.
Fig. 59 Structure of A-D control register
A-D control register
(ADCON : address 0034
16
)
Analog input pin selection bits
000: P6
0
/AN
0
001: P6
1
/AN
1
010: P6
2
/AN
2
011: P6
3
/AN
3
100: P6
4
/AN
4
101: P6
5
/AN
5
110: P6
6
/AN
6
111: P6
7
/AN
7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
V
REF
input switch bit
0: OFF
1: ON
AD external trigger valid bit
0: AD external trigger invalid
1: AD external trigger valid
Interrupt source selection bit
0: Interrupt request at A-D
conversion completed
1: Interrupt request at ADT
input falling
DA output enable bit
0: DA output disabled
1: DA output enabled
b7
b0
C
A-D control circuit
A-D conversion register
Resistor ladder
AV
SS
V
REF
Comparator
ADT/A-D interrupt
request
b7
b0
A-D control register
3
P6
0
/AN
0
P6
1
/AN
1
P6
2
/AN
2
P6
3
/AN
3
P6
4
/AN
4
P6
5
/AN
5
P6
6
/AN
6
P6
7
/AN
7
8
P7
7
/ADT
Data bus
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