参数资料
型号: M38C29MCA-XXXHP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件页数: 13/104页
文件大小: 1327K
代理商: M38C29MCA-XXXHP
Rev.2.00
May 28, 2004
page 14 of 100
38C2 Group (A Version)
I/O PORTS
Direction Registers
The I/O ports P0–P6 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When “0” is written to the bit of the direction register, the correspond-
ing pin becomes an input pin. As for ports P0–P2, when “1” is written
to the bit of the direction register and the segment output disable
register, the corresponding pin becomes an output pin. As for ports
P3–P6, when “1” is written to the bit of the direction register, the
corresponding pin becomes an output pin.
If data is read from a pin set to output, the value of the port latch is
read, not the value of the pin itself. Pins set to input are floating. If a
pin set to input is written to, only the port output latch is written to and
the pin remains floating.
Pull-up Control
Each individual bit of ports P0–P2 can be pulled up with a program
by setting direction registers and segment output disable registers 0
to 2 (addresses 0FF816 to 0FFA16).
The pin is pulled up by setting “ 0”
to the direction register and
“ 1”
to
the segment output disable register.
By setting the PULL register (address 0FF116), ports P3–P6 can con-
trol pull-up with a program.
However, the contents of PULL register do not affect ports pro-
grammed as the output ports.
Fig. 11 Structure of PULL register and segment output disable register
Fig. 10 Structure of ports P0 to P2
Segment output
disable register
Direction register
“ 0”
“1”
“ 0”“
1”
Input port
No pull-up
Segment
output
Port output
Input port
Pull-up
Initial state
P30– P33 pull-up
P34– P37 pull-up
P40– P43 pull-up
P44– P47 pull-up
P50– P53 pull-up
P54– P57 pull-up
P60– P62 pull-up
Not used (return “ 0”
when read)
PULL register
(PULL : address 0FF116)
b7
b0
P00 pull-up
P01 pull-up
P02 pull-up
P03 pull-up
P04 pull-up
P05 pull-up
P06 pull-up
P07 pull-up
Segment output disable register 0
(SEG0 : address 0FF816)
b7
b0
Notes 1: The PULL register and segment output disable register affect only ports
programmed as the input ports.
2: When the VL pin input selection bit (VLSEL) of the LCD power control
register (address 0038 16) is “ 1” , settings of P2
6
and P2 7 are invalid.
0: No pull-up
1: Pull-up
P10 pull-up
P11 pull-up
P12 pull-up
P13 pull-up
P14 pull-up
P15 pull-up
P16 pull-up
P17 pull-up
b7
b0
Segment output disable register 1
(SEG1 : address 0FF916)
P20 pull-up
P21 pull-up
P22 pull-up
P23 pull-up
P24 pull-up
P25 pull-up
P26 pull-up
P27 pull-up
b7
b0
Segment output disable register 2
(SEG2 : address 0FFA16)
0: No pull-up
1: Pull-up
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