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参数资料
| 型号： | M38C80M6-XXXFP |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | RES 75-OHM 1% 0.125W 200PPM THK-FILM SMD-1206 TR-7-PA |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 20/51页 |
| 文件大小： | 874K |
| 代理商： | M38C80M6-XXXFP |
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20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
TIMERS
The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and
timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2,
and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00
16
”, an
underflow occurs at the next count pulse and the corresponding timer
latch is reloaded into the timer and the count is continued. When a
timer underflows, the interrupt request bit corresponding to that timer
is set to “1”.
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
Fig. 16 Timer block diagram
“
10
”
Timer Y stop
i
m
Falling edge detection
Period measure-
ment mode
T
r
i
m
q
e
u
r
s
Y
t
i
n
t
e
r
r
u
p
t
e
e
Pulse width HL continuously
measurement mode
Rising edge detection
“
00
”
,
“
01
”
,
“
11
”
Timer Y operating
T
r
i
m
q
e
u
r
s
X
t
i
n
t
e
r
r
u
p
t
e
e
Timer X (low) (8)
T
i
m
e
r
X
(
h
i
g
h
)
(
8
)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)
Q
Q
T
S
“
0
”
“
1
”
“
1
0
”
f(
(
X
I
f
(
N
)
/
N
)
1
6
/
X
C
I
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
“
0
“
00
”
,
“
01
”
,
“
11
”
C
e
0
N
d
T
e
R
0
s
a
i
c
t
c
t
i
h
v
e
b
i
g
w
t
C
e
N
d
T
e
R
0
s
a
i
c
t
c
t
i
h
v
e
b
i
g
w
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
T
i
m
e
r
2
l
a
t
c
h
(
8
)
Timer 2 (8)
“
1
/
I
”
“
1
”
f
(
X
C
I
N
)
/
3
2
T
r
i
m
q
e
u
r
s
1
t
i
n
t
e
r
r
u
p
t
e
e
Data bus
I
n
t
e
r
n
a
l
c
l
o
c
k
φ
=
X
C
I
N
d
i
v
i
d
e
d
b
y
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
C
r
e
N
q
T
u
R
e
0
s
i
n
t
e
r
r
u
p
t
t
CNTR1 interrupt
request
Timer Y operating mode bits
“
0
0
”
,
“
0
1
”
,
“
1
0
”
“
11
”
0
”
,
“
1
1
”
Timer X operating
mode bits
P
4
3
/
C
N
T
R
1
/
B
E
E
P
-
P
4
2
/
C
N
T
R
0
/
B
E
E
P
+
“
”
“
1
”
Pulse width
mode
B
u
z
z
e
r
o
u
t
p
u
t
m
o
d
e
P4
2
latch
P
4
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
BEEP- valid bit
f(X
CIN
“
0
”
“
1
”
f
(
X
I
N
)
T
s
i
m
e
l
e
c
r
t
i
X
o
n
c
o
b
u
i
t
n
t
s
o
u
r
c
e
e
f
(
X
C
I
N
)
/
3
2
Timer X operating
Timer X stop control bit
Timer X write control bit
T
i
m
e
r
X
(
h
i
g
h
)
l
a
t
c
h
(
8
)
1
active
CNTR
P
4
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P4
3
latch
f(X
IN
)/16
(f(X
CIN
)/16 in low-speed mode
)
“
1
”
“
0
”
T
i
m
e
r
Y
(
l
o
w
)
(
8
)
Timer Y (high) (8)
T
e
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)
Timer Y (low) high (8)
f(X
IN
)/16
(f(X
CIN
)/16 in low-speed mode
)
Timer 1 count source
selection bit
T
r
i
m
q
e
u
r
s
2
t
i
n
t
e
r
r
u
p
t
e
e
T
r
i
m
q
e
u
r
s
3
t
i
n
t
e
r
r
u
p
t
e
e
f(
(
X
I
f
(
N
)
1
N
)
6
/
X
C
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
s
i
m
e
l
e
c
0
r
t
”
i
2
o
n
c
o
b
u
i
t
n
t
s
o
u
r
c
e
e
“
Timer 2 write control bit
Timer 3 latch (8)
i
m
e
r
T
3
(
8
)
“
0
”
T
i
m
e
r
1
l
a
t
c
h
(
8
)
Timer 1 (8)
“
1
”
“
0
”
Timer 3 count source
selection bit
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