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参数资料
| 型号： | M38C81E1-XXXFP |
| 厂商： | Mitsubishi Electric Corporation |
| 元件分类： | Codec |
| 英文描述： | Low-Power Stereo CODEC with HP Amplifier 28-TSSOP 0 to 70 |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 17/51页 |
| 文件大小： | 874K |
| 代理商： | M38C81E1-XXXFP |
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17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
INTERRUPTS
Interrupts occur by fifteen sources: six external, eight internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are
“
1
”
and the interrupt disable flag is
“
0
”
.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The processing being executed is stopped.
2.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3.The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4.The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“
1
”
.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A
16
)
Timer X mode register (address 27
16
)
Timer Y mode register (address 28
16
)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: AD control regsiter (address 31
16
)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to
“
0
”
(disabled).
Set the interrupt edge select bit (active edge switch bit) or the inter-
rupt source select bit to
“
1
”
.
Set the corresponding interrupt request bit to
“
0
”
after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to
“
1
”
(enabled).
Interrupt Source
Reset
(Note 2)
INT
0
INT
1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
0
CNTR
1
Timer 1
Key input (Key-
on wake-up)
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Vector Addresses
(Note 1)
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE1
16
FFDF
16
FFDD
16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling edge of
INT
0
intput
At detection of either rising or falling edge of
INT
1
input
At completion of serial I/O data reception
At completion of serial I/O transmission shift
or when transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or falling edge of
CNTR
0
input
At detection of either rising or falling edge of
CNTR
1
input
At timer 1 underflow
At falling of port P2 (at input) input logical level
AND
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Valid when A-D conversion interrupt
is selected
Non-maskable software interrupt
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE0
16
FFDE
16
FFDC
16
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
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