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参数资料
| 型号： | M38C81E7-XXXFP |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 30/51页 |
| 文件大小： | 874K |
| 代理商： | M38C81E7-XXXFP |
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30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Fig. 28 Structure of LCD control register
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixel
16
68 dots
(5
7 dots + cursor 2 lines)
32
52 dots
(5
7 dots + cursor 4 lines)
16
32
LCD Controller/Driver Function
The controller/driver performs the bias control and the time sharing
control by the LCD control registers 1, 2 (LC1, LC2), and the LCD
mode register (LM). The data of corresponding LCDRAM is output
from the segment pins according to the output timing of the common
pins.
The 38C8 group has the voltage multiplier only for LCD in addition to
LCD controller/driver .
[LCD mode register (LM)] 0039
16
The LCD mode register is used for setting the LCD controller/driver
according to the LCD panel used.
[LCD control register 1 (LC1)] 0037
16
The LCD control register 1 controls the voltage multiplier and built-in
resistance.
[LCD control register 2 (LC2)] 0038
16
The LCD control register 2 is read-only. Setting
“
1
”
to bit 5 makes
built-in resistance low resistance, and can raise drivability of the seg-
ment pins and the common pins.
Note:
When executing the STP instruction while operating LCD, ex-
ecute the STP instruction after prohibiting LCD (set
“
0
”
to bit 3
of the LCD mode regsiter).
LCD control register 1
(LC1: address 0037
16
)
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Note 3:
LCDCK is a clock for a LCD timing controller.
Internal clock
φ
is X
CIN
divided by 2 in the low-speed mode.
When selecting 32 duty, functions of pins 130 to 142 become COM16 to COM23,
and functions of pins 75 to 82 become COM24 to COM31.
N
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“
1
”
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)
Duty ratio selsection bit
1 : 32 duty (use COM
0
–
COM
31
)
0 : 16 duty (use COM
0
–
COM
15
)
Not used
(Do not write
“
0
”
to this bit.)
LCD display RAM address selection bit
0 : 3 page
1 : 0 page
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : A type
1 : B type
LCDCK division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit
(Note 3)
0 : f(X
IN
)/1024
1 : f(X
CIN
)/16
L
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)
Drivability selection bit 1
0 : Normal (Drivability selection
bit 2 valid)
1 : Restraint
(
Note 1)
LCD control register 2
(LC2: address 0038
16
)
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