28
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)] 0032
16
,
0033
16
The A-D conversion registers are read-only registers that contain the
result of an A-D conversion. During A-D conversion, do not read these
registers.
[A-D Control Register (ADCON)] 0031
16
The A-D control register controls the A-D conversion process. Bits 0
to 2 are analog input pin selection bits. Bit 3 is an A-D conversion
completion bit and
“
0
”
during A-D conversion, then changes to
“
1
”
when the A-D conversion is completed. Writing
“
0
”
to this bit starts
the A-D conversion. When bit 5, which is the AD external trigger valid
bit, is set to
“
1
”
, A-D conversion is started even by a rising edge or
falling edge of an ADT input.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD interrupt
request bit to
“
1
”
.
Because the comparator consists of a capacitor coupling, a deficient
conversion speed may cause lack of electric charge and make the
conversion accuracy worse. When A-D conversion is performed in
the middle-speed mode or the high-speed mode, set f(X
IN
) to at least
500 kHz.
In the low-speed mode, A-D conversion is performed by using the
built-in self-oscillation circuit. Therefore, there is no limitation in
the lower bound frequency of f(X
IN
).
Trigger Start
When using the A-D external trigger, set the port shared with the
ADT pin to input. The polarity of INT1 interrupt edge also applies to
the A-D external trigger. When the INT1 interrupt edge polarity is
switched after an external trigger is validated, an A-D conversion
may be started.
Fig. 26 A-D converter block diagram
Fig. 25 Structure of A-D control register
Resistor ladder
The resistor ladder outputs the comparison voltage by dividing the
voltage between V
DD
and V
SS
by resistance.
Channel Selector
The channel selector selects one of the ports P3
3
/A
IN3
–
P3
0
/A
IN0
and
ports P1
0
/A
IN4
–
P1
3
/A
IN7
, and inputs it to the comparator.
A
(
A
-
D
D
C
A
c
o
O
n
N
a
0
0
0
1
1
1
1
t
r
l
o
o
:
l
a
g
0
1
0
1
0
1
0
1
r
d
i
:
:
:
:
:
:
:
:
e
g
r
p
P
P
P
P
P
P
P
P
i
e
u
3
0
/
3
1
/
3
2
/
3
3
/
1
0
/
1
1
/
1
2
/
1
3
/
s
t
e
s
p
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
r
i
d
s
t
0
n
N
N1
N2
N3
N4
N5
N6
N7
0
0
3
s
1
1
e
l
6
)
c
n
0
n
e
t
i
o
n
b
i
t
s
0
0
1
1
0
0
1
1
b7
b0
b
9 b
7
8 b
7 b
6 b
5 b4 b
3 b
2
b9 b8
7 b
6 b5 b
4 b
3 b
2
8-bit read (Read only address 0032
16
.)
A
-
D
c
o
n
v
e
r
s
i
(
o
A
n
D
r
L
e
:
g
i
s
d
t
e
d
r
r
e
(
l
o
s
w
0
-
o
0
r
3
d
2
1
e
r
6
)
)
A
s
1
0
-
b
i
t
r
e
a
d
(
R
e
a
d
a
d
d
r
e
s
s
0
0
3
3
1
6
f
i
r
s
t
b7
.
)
N
o
t
e
:
H
i
g
h
-
o
r
d
e
r
6
b
i
t
s
o
f
a
d
d
r
e
s
s
0
0
3
3
1
6
b
e
c
o
m
e
s
“
0
”
a
t
r
e
a
d
i
n
g
.
1 b
0
b
0
A-D conversion register (low-order)
(ADL: Address 0032
16
)
A
-
D
c
o
n
v
e
r
s
i
o
(
n
r
e
H
g
:
i
A
s
t
d
e
r
r
(
e
h
s
i
g
s
h
0
-
o
0
r
3
d
3
1
e
r
6
)
)
A
D
d
b
0
b7
b
0
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
o
t
u
s
e
d
(
r
e
t
u
r
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
A
0
1
D
e
A
A
x
-
-
t
D
D
e
r
e
e
n
a
x
x
l
e
e
t
r
r
r
n
n
i
g
a
a
g
l
l
e
t
t
r
i
i
g
g
v
a
g
g
l
i
r
r
d
i
v
b
n
a
i
v
t
:
:
t
t
r
r
e
e
a
l
i
l
i
d
d
N
n
“
0
”
w
h
e
n
r
e
a
d
)
A-D control circuit
V
S
S
b
7
b0
3
P
P
P
P
P
P
P
P
3
0
/
3
1
/
3
2
/
3
3
/
1
0
/
1
1
/
1
2
/
1
3
/
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
N
N1
N2
N3
N4
N5
N6
N7
0
10
P4
1
/INT
1
/ADT
(H
)
(L)
V
C
C
D
a
t
a
b
u
s
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
A-D conversion register
Resistor ladder
Comparater
A-D interrupt request
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A-D conversion register