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参数资料
| 型号： | M38K29RFS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, CPGA100 |
| 封装： | 0.65 MM PITCH, PGA-100 |
| 文件页数： | 17/25页 |
| 文件大小： | 1451K |
| 代理商： | M38K29RFS |
38K2 Group
Rev.3.00
Oct 15, 2006
page 22 of 147
REJ03B0193-0300
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Fig. 20 Block diagram of UART serial I/O
Fig. 21 Operation of UART serial I/O function
System clock
1/4
OE
PE FE
1/16
Data bus
Receive buffer register
Address 002616
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Address 0FE216
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Address 002616
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 002716
STdetector
SP detector
UART control register
Address 0FE116
Character length selection bit
Address 0FE016
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 control register
P42/EXTC/SCLK
Serial I/O status register
P40/EXDREQ/RxD
P41/EXDACK/TxD
TSC=0
TBE=1
RBF=0
TBE=0
RBF=1
ST
D0
D1
SP
D0
D1
ST
SP
TBE=1
TSC=1
ST
D0
D1
SP
D0
D1
ST
SP
Transmit buffer write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output TXD
Serial input RXD
Receive buffer read signal
Transmit or receive clock
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